MPC8610EC datasheet(56/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

2.17.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express.

The following sections describe the SerDes reference clock requirements and some application information.

2.17.2.1

SerDes Reference Clock Receiver Characteristics

Figure 30 shows a receiver reference diagram of the SerDes reference clocks.

•

The supply voltage requirements for XnVDD are specified in Table 2 and Table 3.

•

SerDes reference clock receiver reference circuit structure

—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 30.

Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-

Ω termination to SGND followed by

on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and

single-ended mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the

maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage

is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the

following bullet for more detail), since the input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)

while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle

can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that

each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage

at 400 mV.

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50

Ω to SGND DC, or it

exceeds the maximum input current limitations, then it must be AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

Figure 30. Receiver of SerDes Reference Clocks

Input

Amp

n_REF_CLK

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