AD2437 datasheet(22/42 Pages) AD

22 / 42 page

Rev. 0

Page 22 of 42

July 2023

AD2437

Serial Peripheral Interface (SPI) Port—Master Timing

Table 10 and Figure 20 describe serial peripheral interface (SPI) port master operations.

Table 10. Serial Peripheral Interface (SPI) Port—Master Timing

IOVDD = 1.8 V

IOVDD = 3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tSMISO

Data Input Valid to SCK Sample Edge (Data Input Setup)

18.5

17.5

tHMISO

SCK Sample Edge to Data Input Invalid (Data Input Hold)

5.50

6.75

Switching Characteristics

tSCKM

1 Measured at fSCKM = 1/tSCKM = 12.288 MHz. Specification scales with fSCKM.

SCK Period

80.3

80.5

fSCKHM

SCK High Period

32.75

39.5

tSCKLM

SCK Low Period

37.0

39.7

tDMOSI

SCK Drive Edge to Data Out Valid (Data Out Delay)

9.00

3.25

tHDMOSI

SCK Drive Edge to Data Out Invalid (Data Out Hold)

0.5

tSSSM

SPISSELn Assertion to First SCK Edge

75.75

77.00

tHSSM

Last SCK Edge to SPISSELn Deassertion

35.50

36.75

tSSPWM

SPISSELn Pulse Width High (Inactive State Between Transfers)

11.25

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