AD2437

Rev. 0

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Page 5 of 42

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July 2023

Note in Figure 4, both downstream and upstream samples are

named for the frame where they enter the A2B system as follows:

•I2S/TDM data received by the main node transceiver in

superframe M creates downstream data M and is transmit-

ted over the A2B bus in the next superframe.

•I2S/TDM data received by the subordinate node transceiv-

ers in superframe N creates upstream data N and is

transmitted over the A2B bus in the next superframe.

• Data received via the A2B bus is transmitted on the

I2S/TDM interface of an A2B transceiver in the following

superframe.

• Data transmitted across the A2B bus (from any node to any

node) has two frames of latency plus any internal delay that

has accumulated in the transceivers, as well as delays due to

wire length. Therefore, overall latency is slightly over two

samples (<50 μs at 48 kHz sample periods) from the

I2S/TDM interface in one A2B transceiver to the I2S/TDM

interface of another A2B transceiver.

To support and extend the A2B bus functions and performance,

the transceivers have additional features, as described in the fol-

lowing sections.

I2C INTERFACE

The I2C interface in the transceiver provides access to the inter-

nal registers. It has the following features:

• Target functionality in the A2B main node

• Controller or target functionality in the A2B subordinate

node

• Multi-controller support in the A2B subordinate node

• 100 kbps, 400 kbps, or 1Mbps rate operation

• 7-bit addressing

• Single-word and burst mode read and write operations

•Clock stretching

All transceivers can be accessed by a locally connected processor

using the 7-bit I2C device address (BASE_ADDR) established by

the logic levels applied to the ADR2 and ADR1 pins at power-

on reset, thus providing for up to four I2C controller devices

connecting to the same I2C bus. A subordinate configured

transceiver recognizes only this I2C device address. A main con-

figured transceiver, however, also recognizes a second I2C

device address for remote access to subordinate nodes and

remote peripherals over the A2B bus (BUS_ADDR). The least

significant bit (LSB) of the 7-bit device address determines

whether an I2C data exchange uses the BASE_ADDR (bit 1 = 0)

to access the local transceiver or BUS_ADDR (bit 1 = 1) to

access a bus node subordinate transceiver and remote peripher-

als through a main configured transceiver. See the AD2437 A2B

Transceiver Technical Reference for details.

I

2S/TDM INTERFACE

The I2S/TDM serial port operates in full-duplex mode, where

both the transmitter and receiver operate simultaneously using

the same critical timing bit clock (BCLK) and synchronization

(SYNC) pins. A2B main transceivers receive the timing signals

from BCLK and SYNC pins driven by the host device. A2B sub-

ordinate transceivers generate the timing signals on the BCLK

and SYNC output pins. The I2S/TDM port features:

• Programmable clock and frame sync timing and polarity

• Numerous TDM operating modes

• 16- or 32-bit data width

•I2S TX/RX crossbar to associate specific TDM data chan-

nels with specific A2B slots

• Simultaneous operation with PDM port

The I2S/TDM/PDM port includes five programmable data pins

(SIO0-SIO4) which can be configured to exchange any combi-

nation of up to two PDM streams (SIO0/1 only) and up to five

I2S/TDM streams, with a maximum of four I2S/TDM streams in

the same direction (see Table 2).

Table 2. SIO Pin Mapping1

A2B_PDMCTL.PDM1EN /PDM0EN

Pin

00

01

10

11

SIO0

DRX0

PDM0

DRX0

PDM0

SIO1

DRX1, DTX3

DRX0, DTX3

PDM1

PDM1

SIO2

DRX2, DTX2

DRX1, DTX2

DRX1, DTX2

DRX0, DTX2

SIO3

DRX3, DTX1

DRX2, DTX1

DRX2, DTX1

DRX1, DTX1

SIO4

DTX0

DTX0

DTX0

DTX0

1 Pin mapping of I2S/TDM DTXn and DRXn depends on A2B_PDMCTL and A2B_I2SCFG registers. See the AD2437 A2B Transceiver Technical Reference for details on pin

mappings.