AD2437 datasheet(33/42 Pages) AD

33 / 42 page

AD2437

Rev. 0

Page 33 of 42

July 2023

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 34

shows the measurement point for ac measurements (except out-

put enable/disable). The measurement point, VMEAS, is VIOVDD/2

for VIOVDD (nominal) = 3.3 V.

Output Enable Time Measurement

Output pins are considered enabled when they make a transi-

tion from a high impedance state to the point when they start

driving.

The output enable time, tENA, is the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving, as shown on the right side of

Figure 35. If multiple pins are enabled, the measurement value

is that of the first pin to start driving.

Output Disable Time Measurement

Output pins are considered disabled when they stop driving,

enter a high impedance state, and start to decay from the output

high or low voltage. The output disable time, tDIS, is the interval

from when a reference signal reaches a high or low voltage level

to the point when the output stops driving, as shown on the left

side of Figure 35.

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 36). VLOAD is equal

to VIOVDD/2. Figure 37 through Figure 40 show how output rise

time varies with capacitance. The delay and hold specifications

given must be derated by a factor derived from these figures.

The graphs in Figure 37 through Figure 40 cannot be linear out-

side the ranges shown.

Figure 33. Digital I/O Drivers (DS1, 3.3 V IOVDD)

Figure 34. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

1.0

2.0

3.0

4.0

–40

VOL

IOVDD = 3.6V @ – 40°C

IOVDD = 3.3V @ 25°C

IOVDD = 3.0V @ 125°C

– 20

– 60

0.5

1.5

2.5

3.5

SOURCE VOLTAGE (V)

VOH

INPUT

OUTPUT

VMEAS

Figure 35. Output Enable/Disable

Figure 36. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

ZO = 50

(impedance)

TD = 4.04

r 1.18 ns

2pF

TESTER PIN ELECTRONICS

0.5pF

400

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

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