Rev. 0

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Page 17 of 42

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July 2023

AD2437

TIMING SPECIFICATIONS

All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.

Clock and Reset Timing

Table 4 and Figure 15 describe clock and reset operations.

I2C Port Timing

The transceiver conforms to the I2C specification v2.1.

Table 4. Clock and Reset Timing

Parameter

Min

Typ

Max

Unit

Timing Requirements

fSYNCM

SYNC Pin Input Frequency Continuous Clock

44.1 kHz SYNC Input

43.7

44.1

44.5

kHz

48 kHz SYNC Input

47.5

48.0

48.5

kHz

tSYNCIJ1

SYNC Pin Input Jitter RMS TIE

1

1 Maximum allowed jitter which does not degrade THD + N performance in the last subordinate node.

1.0

ns

tMCLKIJ1

Main Node Bit Clock Input Jitter RMS TIE1

1.0

ns

tACCESS

Device Access Time After Reset2

2 The time it takes to access local registers via I2C/SPI once the reset pin is deasserted and the power supplies are stable.

1.5

ms

tRST

Reset Width3

3 Valid only when all the power supplies are stable. See Figure 15 for tRST.

10

μs

tDNSYNCR

4

4 Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset.

Delay From First Missed SYNC Input to Reset



(A2B Main Node)

31

32

33

tSYNCM

tDNSCFR

4, 5

5 Add 1024 if SUSTAIN = 1.

Delay From First Missed SCF to Reset



(A2B Subordinate Node)

31

32

33

tSYNCM

tPLK

PLL Lock Time

7.5

ms

fSYSBCLK

A2B Bus Clock

1024 × fSYNCM

kHz

tSYSBCLK

Bit-Period of A

2B Bus Clock

1/(1024 × fSYNCM)ns

Figure 15. Reset Timing

tRST

RST

tACCESS