Rev. 0

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Page 18 of 42

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July 2023

AD2437

I2S/TDM Port Timing

Table 5, Table 6, Figure 16, and Figure 17 describe I2S/TDM port operations. Note the following:

• The SIO0-SIO4 data pins on the I2S/TDM port can be configured for up to two PDM streams and up to five I2S/TDM streams, with a

maximum of four I2S/TDM streams in the same direction. DTXn includes the DTX0, DTX1, DTX2, and DTX3 pins; and DRXn

includes DRX0, DRX1, DRX2, and DRX3 in Table 5.

•The I2S/TDM target timing applies to the A2B main transceiver and the A2B subordinate transceiver operating in parallel bus mode.

•The I2S/TDM controller timing applies to the A2B subordinate transceiver.

Table 5. I2S/TDM Port—Controller Timing

IOVDD = 1.8 V

IOVDD = 3.3 V

Unit

Parameter

Min

Max

Min

Max

Timing Requirements

tRISM

DRXn Input Setup Before BCLK Sample Edge

1.0

1.5

ns

tRIHM

DRXn Input Hold After BCLK Sample Edge

5.5

2.0

ns

Switching Characteristics

fBCLKM

BCLK Output Frequency1

1 When VIOVDD = 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I2S devices. The timing violations are

observed when the subordinate transceiver I2S/TDM port is receiving and the main transceiver I2S/TDM port is transmitting. In this case, the maximum BCLK frequency of

50 MHz cannot be achieved.

25.0

50.0

MHz

tBCLKMOJ

BCLK Output Jitter (RMS Cycle to Cycle)

at fBCLKSM = 12.288 MHz

100

100

ps

at fBCLKSM = 24.576 MHz

100

100

ps

tSOL/tSOH

Transmit or Receive BCLK Duty Cycle

49%

51%

49%

51%

tBCLKM

tSOJ

SYNC Output Jitter (RMS Cycle to Cycle)

Normal Mode 48 kHz

2.25

2.25

ns

Increased Data Rate 2× SYNC

1.25

1.25

ns

Increased Data Rate 4× SYNC

1.00

1.00

ns

tSOD

SYNC Output Delay After BCLK Drive Edge

9.75

9.75

ns

tSOHD

SYNC Output Hold After BCLK Drive Edge

3.0

4.5

ns

tDODM

DTXn Output Delay After BCLK Drive Edge

10.25

9.75

ns

tDOHM

DTXn Output Hold After BCLK Drive Edge

5.5

6.0

ns

Figure 16. I2S/TDM Port—Controller Timing

DRIVE EDGE

SAMPLE EDGE

tSOHD

tRIHM

tDODM

tDOHM

tSOL

tSOD

tRISM

TRANSMIT DATA

(DTXn) CHANNEL

RECEIVE DATA

(DRXn) CHANNEL

SYNC

BCLK

MSB - 1

MSB - 1

MSB

MSB

/tSOH