AD2437 datasheet(11/42 Pages) AD

11 / 42 page

Rev. 0

Page 11 of 42

July 2023

AD2437

Bus Voltage

Chip Reset Assertion Voltage Threshold4

VRST_VIN

VVIN dropping, LVI Mode = 0, 1

2.49

2.73

VRST_DVDD

VDVDD dropping

1.1

1.5

VRST_IOVDD

VIOVDD dropping

1.0

1.5

VRST_TRXVDD

VTRXVDD dropping, LVI Mode = 0, 1

2.2

2.8

Chip Reset Deassertion Voltage Threshold5

VRSTN_VIN

VVIN rising, LVI Mode = 0, 1

2.76

3.10

VRSTN_DVDD

VDVDD rising

1.50

1.65

VRSTN_IOVDD

VIOVDD rising

1.20

1.62

VRSTN_TRXVDD

VTRXVDD rising, LVI Mode = 0, 1

2.53

3.05

Voltage Regulator (VREG1, VREG2)

VVOUT1

VREG1 Output Voltage

1.80

1.90

1.98

VVOUT2

VREG2 Output Voltage

3.15

3.30

3.45

IVOUT1

VREG1 Output Current

100

IVOUT2

VREG2 Output Current

100

IVOUT1 + IVOUT2

1307

V

OUT1_LNREG

VVOUT1 Line Regulation

VVIN = 3.13 V to 3.47 V,

IVOUT1 = 100 mA, LVI_MODE = 1

5mV

V

OUT1_LNREG

VVOUT1 Line Regulation

VVIN = 3.7 V to 4.9 V,

IVOUT1 = 100 mA

5mV

V

OUT2_LNREG

VVOUT2 Line Regulation

VVIN = 3.7 V to 6.3 V,

IVOUT2 = 100 mA

V

OUT1_LNREG

VVOUT1 Line Regulation

VVIN = 3.7 V to 9 V,

IVOUT1 = 40 mA

6mV

V

OUT2_LNREG

VVOUT2 Line Regulation

VVIN = 3.7 V to 9 V,

IVOUT2 = 50 mA

8mV

V

OUT1_LDREG

VVOUT1 Load Regulation

VVIN = 3.13 V,

IVOUT1=1mA to 100 mA, LVI_MODE = 1

V

OUT1_LDREG

VVOUT1 Load Regulation

VVIN = 3.7 V,

IVOUT1 = 1 mA to 40 mA

V

OUT2_LDREG

VVOUT2 Load Regulation

VVIN = 3.7 V,

IVOUT2 = 1mA to 50 mA

V

OUT1_LDREG

VVOUT1 Load Regulation

VVIN = 3.7 V,

IVOUT1= 1mA to 100 mA

V

OUT2_LDREG

VVOUT2 Load Regulation

VVIN = 3.7 V,

IVOUT2 = 1mA to 100 mA

CLoad1

VREG1 Load Capacitance

1.8

μF

CLoad2

VREG2 Load Capacitance

3.9

μF

Parameter

Conditions

Min

Typ

Max

Unit

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