PSD913F2 datasheet(53/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

9.4.5 Ports A and B – Functionality and Structure

Ports A and B have similar functionality and structure, as shown in Figure 20. The two

ports can be configured to perform one or more of the following functions:

t MCU I/O Mode

t GPLD Output – Combinatorial PLD outputs can be connected to Port A or Port B.

t PLD Input

– Input to the PLDs.

t Latched Address output – Provide latched address output per Table 30.

t Address In – Additional high address inputs, may be latched by ALE.

t Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to fast slew rate,

pins PA[7:4] and PB[7:4] can be configured to Open Drain

Mode.

t Data Port – Port A only, connect to non-multiplexed 8-bit data bus.

The

PSD9XX

Functional

Blocks

(cont.)

9.4.4 Port Data Registers

The Port Data Registers, shown in Table 28, are used by the microcontroller to write data

to or read data from the ports. Table 28 shows the register name, the ports having each

described below.

9.4.4.1 Data In

Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input

is read through the Data In buffer.

9.4.4.2 Data Out Register

Stores output data written by the MCU in the MCU I/O output mode. The contents of the

product term is set to “1”. The contents of the register can also be read back by the

microcontroller.

Port

MCU Access

Data In

A,B,C,D

Read – input on pin

Data Out

A,B,C,D

Write/Read

Table 28. Port Data Registers

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