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PSD913F2 bảng dữ liệu(PDF) 78 Page - STMicroelectronics

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PSD913F2 bảng dữ liệu(HTML) 78 Page - STMicroelectronics

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PSD9XX Family
Preliminary Information
74
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
-12
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
26
26
30
tAVLX
Address Setup Time
(Note 1)
9
10
12
ns
tLXAX
Address Hold Time
(Note 1)
9
12
14
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
17
20
25
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
17
20
25
ns
t DVWH
WR Data Setup Time
(Note 3)
45
45
50
ns
t WHDX
WR Data Hold Time
(Note 3)
7
8
10
ns
t WLWH
WR Pulse Width
(Note 3)
46
48
53
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
10
12
17
ns
tWHAX2
Trailing Edge of WR to DPLD Address
(Notes 3 and 4)
0
0
0
ns
Input Invalid
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
33
35
40
ns
tAVPV
Address Input Valid to Address
(Note 2)
33
35
40
ns
Output Delay
Write Timing (3 V Versions)
NOTES: 1. Any input used to select an internal PSD813F function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)
-12
-15
-20
Fast
Slew
PT
TURBO
Rate
Symbol
Parameter
Conditions Min
Max
Min
Max
Min
Max
Aloc
OFF
(Note 1)
Unit
tPD
PLD Input Pin/Feedback
to PLD Combinatorial
40
45
50
Add 4
Add 20 Sub 6
ns
Output
tARD
PLD Array Delay
Any
25
29
33
Add 4
ns
Micro
⇔Cell
PLD Combinatorial Timing (3 V Versions)



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