| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
PSD913F2 bảng dữ liệu(PDF) 64 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
PSD913F2 bảng dữ liệu(HTML) 64 Page - STMicroelectronics |
|
64 / 94 page ![]() PSD9XX Family Preliminary Information 60 Port C Pin JTAG Signals Description PC0 TMS Mode Select PC1 TCK Clock PC3 TSTAT Status PC4 TERR Error Flag PC5 TDI Serial Data In PC6 TDO Serial Data Out Table 34. JTAG Port Signals The PSD9XX Functional Blocks (cont.) 9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 and PSD954F2) An external reset on the RESET pin will also reset the internal Flash memory state machine. When the Flash is in programming or erase mode, the RESET pin will terminate the programming or erase operation and return the Flash back to read mode in tNLNH-A (minimum 25 µs) time. 9.6 Programming In-Circuit using the JTAG Interface The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be programmed through the JTAG interface. A blank part can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and erase operations. *SR_cod bit in the VM Register are always cleared to zero on power on or warm reset. ** Port Configuration Power On Reset Warm Reset Power Down Mode MCU I/O Input Mode Input Mode Unchanged PLD Output Valid after internal Valid Depend on inputs to PSD configuration PLD (address are bits are loaded blocked in PD mode) Address Out Tri-stated Tri-stated Not defined Data Port Tri-stated Tri-stated Tri-stated Table 33. Status During Power On Reset, Warm Reset and Power Down Mode Register Power On Reset Warm Reset Power Down Mode PMMR0, 2 Cleared to “0” Unchanged Unchanged VM Register* Initialized based on Initialized based on Unchanged the selection in the selection in PSDsoft PSDsoft Configuration Menu. Configuration Menu. All other registers Cleared to “0” Cleared to “0” Unchanged By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note 54 for more details on JTAG In-System-Programming. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |