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PSD913F2 bảng dữ liệu(PDF) 79 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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PSD913F2 bảng dữ liệu(HTML) 79 Page - STMicroelectronics

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Preliminary Information
PSD9XX Family
75
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tNLNH
Warm RESET Active Low Time (Note 1)
300
ns
tOPR
RESET High to Operational Device
300
ns
tNLNH-PO
Power On Reset Active Low Time
1
ms
Warm Reset, will abort and reset Flash
tNLNH-A
programming/erase cycles to Read
25
µs
mode. For PSD9X4FV only.
Reset Pin Timing (3 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
Vstby Detection to Vstbyon Output
High
(Note 1)
20
µs
tBXBL
Vstby Off Detection to Vstbyon
Output Low
(Note 1)
20
µs
Vstbyon Timing (3 V Versions)
NOTE: 1. RESET will not reset Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.
-12
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
tLVDV
ALE Access Time from
Power Down
145
150
200
ns
Maximum Delay from APD Enable
Using
tCLWH
to Internal PDN Valid Signal
CLKIN Input
15
* tCLCL (µs) (Note 1)
µs
Power Down Timing (3 V Versions)
NOTE: 1. tCLCL is the CLKIN clock period.
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)



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