PSD913F2 datasheet(21/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.1.1.3.1 Instructions

An instruction is defined as a sequence of specific operations. Each received byte is

sequentially decoded by the PSD and not executed as a standard write operation. The

instruction is executed when the correct number of bytes are properly received and the

time between two consecutive bytes is shorter than the time-out value. Some instructions

are structured to include read operations after the initial write operations.

The sequencing of any instruction must be followed exactly. Any invalid combination of

instruction bytes or time-out between two consecutive bytes while addressing Flash

memory will reset the device logic into a read array mode (Flash memory reads like a

ROM device).

The PSD9XX main Flash and Secondary Flash support these instructions (see Table 9):

t Erase memory by chip or sector

t Suspend or resume sector erase

t Program a byte

t Reset to read array mode

t Read Main Flash Identifier value

t Read sector protection status

t Bypass Instruction (PSD934F2 and PSD954F2 only)

These instructions are detailed in Table 9. For efficient decoding of the instructions, the

first two bytes of an instruction are the coded cycles and are followed by a command byte

or confirmation byte. The coded cycles consist of writing the data AAh to address X555h

during the first cycle and data 55h to address XAAAh during the second cycle. Address

lines A15-A12 are don’t care during the instruction write cycles. However, the appropriate

sector select signal (FSi or CSBOOTi) must be selected.

The main Flash and the Secondary Flash Block have the same set of instructions (except

Read main Flash ID). The chip selects of the Flash memory will determine which Flash will

receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is

active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.

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