CMV8000 datasheet(19/90 Pages) AMSOSRAM

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CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 18

Functional Description

7.1

Sensor Architecture

Figure 2 shows the architecture of the CMV8000 image sensor. The internal sequencer generates the

necessary signals for image acquisition. Once the acquisition is complete, the image is stored in the

pixel (global shutter) and is then read out row by row. The signal then passes through an analog front

end, where gain can be applied, and an ADC block where the analog to digital conversion is done.

These digital signals then go to the LVDS output stage, to be serialized to 16 parallel output channels.

In the default LVDS configuration, each output channel puts out 224 adjacent columns of the pixel

array in two bursts of 112 pixels to form a row of 3584 pixels. Two additional output channels contain a

double data rate clock signal to sample the pixel data, and a control channel containing the sync

codes which identify when valid pixel data is available.

The on-chip sequencer can be controlled through a four-wire serial interface, which reads and writes

to the sequencer’s control registers. An on-chip temperature sensor can also be read out through this

interface.

7.1.1

Pixel Array

The total pixel array consists of 3584 by 2528 pixels, each with a surface of 5.5 µm by 5.5 µm. Of this

total array, 224 columns and 32 rows contain an electrical black signal, leaving an active image

resolution of 3360 by 2496 pixels. Figure 11 shows the physical layout of the complete pixel array.

The pixels are designed to achieve maximum sensitivity with low noise and good PLS performance.

Microlenses are placed on top of the pixels for improved quantum efficiency.

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