CMV8000 datasheet(31/90 Pages) AMSOSRAM

31 / 90 page

Document Feedback

CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 30

7.3.2

Readout Format

Similar to other CMV products, the data readout is organized in pixels that are aligned using a side-

band control channel.

Low-Level Pixel Timing

●

Data is transferred in words of 10-bit or 12-bit over each channel, with each word containing the

value of a single pixel.

●

Data is transferred LSB first

The figure below shows the timing for the read-out of 10-bit and 12-bit pixel data over one LVDS

output, together with the DDR output clock (OUT_CLK). The D[0] bit is always transferred during the

high phase of the output clock.

Figure 26:

10-Bit Pixel Data

For 10-

bit mode, the time ‘T1’ in Figure 26 will be equal to 1 clock cycle of the IN_LCLK input clock.

When a frequency of 300 MHz (max for 10-bit mode) is applied to IN_LCLK, this results in a 300 MHz

OUT_CLK.

Figure 27:

12-Bit Pixel Data

For 12-

bit mode, the time ‘T2’ in the above figure will be equal to 1 clock cycle of the IN_LCLK input

clock. When a frequency of 300 MHz is used for IN_LCLK (maximum in 12-bit mode), this results in a

300 MHz OUT_CLK.

OUT_CLK

DATA_OUT D[7]

D[8] D[9] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[0] D[1] D[2]

OUT_CLK

DATA_OUT D[10]

D[11] D[12] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[0] D[1] D[2]

CMV8000 bảng dữ liệu(PDF) 31 Page - ams-OSRAM AG