CMV8000 datasheet(24/90 Pages) AMSOSRAM

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CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 23

Figure 14:

Supply Power-Up and Power-Down Sequence

7.2.3

Startup & Reset Sequence

The following sequence should be followed when the sensor is started up.

The input clock should start after the rise time of the supplies. The SYS_RESN pin should be released

about 100 µs after the input clock is stable. The recommended register settings can be uploaded

100 µs after the rising edge on SYS_RESN.

The first F_REQ pulse must not be sent until the SPI upload is completed, plus a settling time. This is

to ensure that the changes programmed in the SPI upload have taken effect before an image is

captured. The settling time is mainly determined by changing the ADC gain, because the voltage the

ramp capacitor has to settle. For typical applications, the gain is changed from the default value of 32

to a value that saturates the ADC output (e.g. 39), the settling time is 8 ms. In extreme cases, when

the ADC gain would be increased to its maximum value of 63, the settling time can increase to 20 ms.

Not respecting the settling time can lead to the first images having an uneven response, or deviating

black level.

Figure 15:

Start-Up Sequence

VDD33

VDD18

VDDPIX

VRST_H

100us

Supplies

IN_LCLK_N/P

SYS_RESN

SPI upload

SPI

F_REQ

Stable time

100us

settling time

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