R34DS0012EU0504 Rev.5.04

Page 23

Sep 18, 2025

ISL73141SEH Datasheet

through an internal oscillator and takes an ensured maximum time of tCONV to complete. Following conversion,

several internal blocks are powered down to reduce power consumption. This phase of power-down is referred to

as NAP mode. The ISL73141SEH stays in NAP mode until the next rising edge of CS where the ISL73141SEH is

fully powered up.

The following is an example of timing calculation in an application operating the ISL73141SEHMF7 at 1Msps.

When deriving timing it is imperative to use the appropriate maximum and minimum specifications. The CS input

must be held high for 40ns (tCSH). The time between the falling edge of CS and the rising edge of BUSY is a

maximum of 30ns (tBUSYLH). The conversion time (tCONV) is a maximum of 660ns. To clock the data out of the

ADC there must be 14 rising edges of SCK (tREADOUT). The 14th SCK falling edge must be coincident with the

rising edge of CS for the subsequent sample. Using the maximum SCK frequency of 50MHz yields:

Note: The 14th SCK edge is coincident with the rising edge of CS so there is only a 1/2 period for the 14th SCK.

To calculate and validate the sample timing use Equation 1:

For a sample rate of 1Msps using the timing calculates to:

5.4

Convert Start (CS) Pin

The convert start input (CS) initiates a conversion in the ISL73141SEH. The input logic level of CS is determined

by the DVCC supply voltage, which operates across a range of 2.2V up to 3.6V. A falling edge on this input starts a

new conversion. The conversion is timed using an internal oscillator. The logic state of the CS pin controls the

state of the SDO pin. A logic high on the CS pin disables the SDO pin driver resulting in a high-impedance state

on the SDO pin. A logic low on the CS pin enables the SDO driver (unless PD is low) and allows data to be read

out following a conversion.

5.5

Power Down (PD) Pin

The ISL73141SEH has a power down pin that is active low (PD). When this pin is asserted the ISL73141SEH is

powered down to ≤50µW of total power dissipation. If PD is asserted during a conversion, the conversion is halted

and the SDO pin is held in high impedance (high-Z). The input logic level of PD is determined by the DVCC supply

voltage, which operates across a range of 2.2V up to 3.6V. There is an internal 500kΩ pull-up resistor connected

to DVCC on this pin.

5.6

Reference Input (REF) Pin

The ISL73141SEH has a voltage reference input that determines the full scale input range. The input voltage

range of this pin is from 1.95V to 3.6V (ISL73141SEHMFN) or 3.9V to 4.2V (ISL73141SEHMF7). Decouple this

pin to ground with a high quality, low ESR 10μF ceramic capacitor. Renesas recommends using a capacitor with a

voltage rating of 10V or greater and to place the capacitor as close as possible to the REF pin.

Use a low noise, low temperature drift reference to drive this pin. Input noise from the input reference directly

impacts the noise performance of the device. Temperature drift of the external reference affects the full scale error

for the over-temperature of the device.

(EQ. 1)

13 20ns 10ns

+



270ns

=

tCYC

tCSH tBUSYLH tCONV tREADOUT

++

+

=

tCYC

40ns 30ns 660ns 270ns

1000ns

=

++

+

=