R34DS0012EU0504 Rev.5.04

Page 5

Sep 18, 2025

ISL73141SEH Datasheet

12

SDO

3

Serial data output. The current conversion result is serially shifted out on this pin on the rising

edges of SCK, MSB first to LSB last. The data stream is composed of 14 bits of conversion

data followed by trailing zeros. Logic Levels are determined by DVCC.

13

DVCC

1

Digital I/O supply. Voltage range on this pin is 2.2V to 3.6V. DVCC is nominally set to the same

supply voltage as the host interface (2.5V or 3.3V). Bypass DVCC to GND with 0.1µF capacitor.

LID

N/A

N/A

Package Lid is internally connected to GND through Pin 14.

Pin Number

Pin

Name

ESD

Circuit

Description

Circuit 1

Pins

1, 3, 5, 13

Circuit 2

Circuit 3

Pins

7, 8, 11

600Ω

DVCC

Pins

9, 12