R34DS0012EU0504 Rev.5.04

Page 4

Sep 18, 2025

ISL73141SEH Datasheet

2.

Pin Information

2.1

Pin Assignments

2.2

Pin Descriptions

Figure 5. Pin Assignments - Top View

Pin Number

Pin

Name

ESD

Circuit

Description

1AVCC

1

Analog supply. The supply range is 3V to 3.6V (ISL73141SEHMFN) or 4.5V to 5.5V

(ISL73141SEHMF7). Bypass this pin to GND with a 10µF ceramic capacitor.

2, 4, 6, 10, 14

GND

-

Analog and digital supply ground. Connect these pins directly to the PCB GND plane. Pin 14

(GND pin) is electrically connected to the package seal ring and lid.

3REF

1

Reference input. The input range of REF is 1.95V to AVCC for the ISL73141SEHMFN and 3.9V

to 4.2V for the ISL73141SEHMF7. The voltage at the REF pin (VREF) defines the input range of

the analog input as 0V to VREF. Bypass REF to GND with a low ESR 10µF ceramic capacitor.

5

AIN

1

Analog input. AIN supports an input voltage range of 0V to VREF.

8CS

2

Convert Start Low input. A falling edge on this input starts a new conversion. The conversion is

timed using an internal oscillator. The device automatically powers down following the

conversion process. The logic state of the CS pin controls the state of the SDO pin. A logic high

on the CS pin disables the SDO pin driver and the SDO pin impedance is Hi-Z. A logic low on

the CS pin enables the SDO driver (unless PD is low) and allows data to be read out following

a conversion.

7PD

2

Power-down low input. When this pin is brought low the ADC enters power-down mode. If this

occurs during a conversion, the conversion is halted and the SDO pin is placed in Hi-Z. Logic

levels are determined by DVCC.

9BUSY

3

Busy output. A logic high indicates a conversion is in progress. The BUSY indicator returns low

following the completion of a conversion. Logic levels are determined by DVCC.

11

SCK

2

Serial data clock input. When CS is low and the BUSY indicator is low, the conversion result is

shifted out on SDO on the rising edges of SCK, Most Significant Bit (MSB) first to Least

Significant Bit (LSB) last. Logic levels are determined by DVCC. SCK should be held low when

it is not being asserted.

Note: The ESD triangular mark is indicative of Pin #1. It is a part of the device

marking and is placed on the lid in the quadrant where Pin #1 is located.

1

2

3

4

5

6

78

9

10

11

12

13

14

AVCC

GND

REF

GND

AIN

GND

PD

CS

BUSY

GND

SCK

SDO

GND

DVCC

Connected to LID