R34DS0012EU0504 Rev.5.04

Page 22

Sep 18, 2025

ISL73141SEH Datasheet

The ISL73141SEH uses the external reference input (REF) as the positive reference and the GND pin of the

device as the negative reference.

5.2

Serial Interface and BUSY

The ISL73141SEH uses a 3-wire serial port interface to communicate with other devices such as microcontrollers

and other external circuitry. A falling edge on CS initiates conversion in the ISL73141SEH. Renesas requires

holding CS high for at least 40ns before initiating the conversion. The conversion is timed by an internal oscillator.

During the conversion process, the BUSY signal is asserted high. When the conversion is complete, BUSY is

de-asserted. Renesas requires holding SCK low during tCONV. When BUSY is de-asserted, the MSB is

immediately available on the SDO pin. Each subsequent rising edge of SCK serially outputs data on SDO from the

MSB-1 to the LSB. The input logic level of CS and SCK is determined by the DVCC supply voltage that operates

across a range of 2.2V up to 3.6V. Similarly, the output voltage level of BUSY is also determined by the DVCC

supply voltage.

5.3

Operational Phases and Timing

The conversion result MSB is available for serial readout at the SDO pin immediately following a completed

conversion. The BUSY indicator flag is high during conversion, and transitions low following completion of the

conversion. When the BUSY indicator flag goes LOW after a conversion, the MSB of the conversion result (B13)

is immediately available at the SDO pin. Subsequent rising edges of SCK shift bits MSB-1 (B12) through the LSB

(B0) to SDO for readout. The output voltage level of SDO is determined by the DVCC supply voltage which

operates across a range of 2.2V up to 3.6V. Figure 57 shows the basic timing of the ISL73141SEH in a conversion

cycle.

The following are the three phases of operation in the ISL73141SEH that are shown in Figure 57.

▪ Acquisition

▪ Conversion

▪ Readout

The Acquisition phase begins immediately following the completion of the conversion. During CS high, the SDO

pin is held in high impedance (high-Z). The falling edge of CS defines the sampling instant of the ISL73141SEH,

initiates a conversion, and also enables the SDO output to a low state. The conversion cycle is internally timed

Figure 57. ISL73141SEH Timing Diagram

12

13

14

12

SCKL

t

SCKH

t

t

SCK

HI-Z

HI-Z

CS

SCK

SDO

CSH

t

t

CONV

READOUT

t

t CYC

B13

B12

B0

B1

B2

B3

t DBUSYLSDOV

tHSDOV

t

DCSLSDOL

tDCSHSDOZ

Serial Data Bits B[13:0] Correspond to the Current Conversion

t

BUSYLH

BUSY

t QUIET

Acquire

Convert

Nap and Readout

Acquire

CSH

t

t

DSCKSDOV