MC68HC908GR4MP datasheet(182/286 Pages) FREESCALE

182 / 286 page

Serial Communications Interface (SCI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

182

Freescale Semiconductor

Figure 18-13. Flag Clearing Sequence

18.8.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditions:

•

Break character detected

•

Incoming data

BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break character on the PE1/RxD pin. In

SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is

cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set

and then reading the SCDR. Once cleared, BKF can become set again only after 1s again appear on

the PE1/RxD pin followed by another break character. Reset clears the BKF bit.

1 = Break character detected

0 = No break character detected

Address:

$0017

Bit 7

654321

Bit 0

Read:

000000

BKF

RPF

Write:

Reset:

00000000

= Unimplemented

Figure 18-14. SCI Status Register 2 (SCS2)

BYTE 1

NORMAL FLAG CLEARING SEQUENCE

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 2

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 3

BYTE 1

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

MC68HC908GR4MP bảng dữ liệu(PDF) 182 Page - Freescale Semiconductor, Inc

MC68HC908GR4MP bảng dữ liệu(HTML) 182 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL