MC68HC908GR4MP datasheet(179/286 Pages) FREESCALE

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I/O Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

179

18.8.3 SCI Control Register 3

SCI control register 3:

•

Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted

•

Enables these interrupts:

–

Receiver overrun interrupts

–

Noise error interrupts

–

Framing error interrupts

•

Parity error interrupts

R8 — Received Bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.

R8 is received at the same time that the SCDR receives the other 8 bits.

When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on

the R8 bit.

T8 — Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted

character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into

the transmit shift register. Reset clears the T8 bit.

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.

Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.

Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE. See

18.8.4 SCI Status Register 1. Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

Address:

$0015

Bit 7

654321

Bit 0

Read:

ORIE

NEIE

FEIE

PEIE

Write:

Reset:

000000

= Unimplemented

= Reserved

U = Unaffected

Figure 18-11. SCI Control Register 3 (SCC3)

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