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STM32H723VG bảng dữ liệu(PDF) 200 Page - STMicroelectronics

tên linh kiện STM32H723VG
Giải thích chi tiết về linh kiện  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32H723VG bảng dữ liệu(HTML) 200 Page - STMicroelectronics

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Electrical characteristics
STM32H723xE/G
200/227
DS13313 Rev 2
Figure 55. MDIO Slave timing diagram
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 111 and Table 112 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 12: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Table 111. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer
mode
-
0
-
120
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fPP =52MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
8.5
9.5
-
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode
tISU
Input setup time HS
-
2.5
-
-
ns
tIH
Input hold time HS
-
0.5
-
-
tIDW(3)
Input valid window (variable window)
-
1.5
-
-
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode
tOV
Output valid time HS
-
-
5.5
6
ns
tOH
Output hold time HS
-
4.5
-
-
MSv40460V1
tsu(MDIO)
tMDC)
th(MDIO)
td(MDIO)



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