STM32H723VG datasheet(188/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

188/227

DS13313 Rev 2

6.3.35

Timer characteristics

The parameters given in Table 102 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

6.3.36

Low-power timer characteristics

The parameters given in Table 103 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 102. TIMx characteristics(1)(2)

1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.

2. Guaranteed by design.

Symbol

Parameter

Conditions(3)

3. The maximum timer frequency on APB1 or APB2 is up to 275 MHz, by setting the TIMPRE bit in the

RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x

Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2.

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APBx prescaler=1

or 2 or 4, fTIMxCLK =

275 MHz

tTIMxCLK

AHB/APBx

prescaler>4, fTIMxCLK =

137.5 MHz

tTIMxCLK

fEXT

Timer external clock

frequency on CH1 to CH4 f

TIMxCLK = 240 MHz

fTIMxCLK/2

MHz

ResTIM

Timer resolution

16/32

bit

tMAX_COUNT

Maximum possible count

with 32-bit counter

65536 ×

65536

tTIMxCLK

Table 103. LPTIMx characteristics(1)(2)

1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.

2. Guaranteed by design.

Symbol

Parameter

Min

Max

Unit

tres(TIM)

Timer resolution time

tTIMxCLK

fLPTIMxCLK Timer kernel clock

137.5

MHz

fEXT

Timer external clock frequency on Input1 and

Input2

fLPTIMxCLK/2

ResTIM

Timer resolution

bit

tMAX_COUNT Maximum possible count

65536

tTIMxCLK

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