TMS320F28076PZP datasheet(96/192 Pages) TI

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7.10.2.1 CMPSS Electrical Data and Timing

Section 7.10.2.1.1 shows the comparator electrical characteristics. Figure 7-35 shows the CMPSS comparator

input referred offset. Figure 7-36 shows the CMPSS comparator hysteresis.

7.10.2.1.1 Comparator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power-up time

500(2)

µs

Comparator input (CMPINxx) range

VDDA

Input referred offset error

Low common mode, inverting input set

to 50 mV

–20

Hysteresis(1)

CMPSS

DAC LSB

Response time (delay from CMPINx input change

to output on ePWM X-BAR or Output X-BAR)

Step response

Ramp response (1.65 V/µs)

Ramp response (8.25 mV/µs)

Common Mode Rejection Ratio (CMRR)

(1)

The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the

CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.

(2)

See the "Analog Bandgap References" advisory of the TMS320F2807x MCUs Silicon Errata .

Note

The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a

CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from

the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal

comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this

time, the comparator could begin to output an incorrect result depending on the value of the other

comparator input.

CTRIPx = 0

CMPINxN or

DACxVAL

CTRIPx = 1

Input Referred Offset

COMPINxP

Voltage

CTRIPx

Logic Level

Figure 7-35. CMPSS Comparator Input Referred Offset

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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