TMS320F28076PZP datasheet(62/192 Pages) TI

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7.9.7.1 External Interrupt (XINT) Electrical Data and Timing

Section 7.9.7.1.1 lists the external interrupt timing requirements. Section 7.9.7.1.2 lists the external interrupt

switching characteristics. Figure 7-16 shows the external interrupt timing.

7.9.7.1.1 External Interrupt Timing Requirements

MIN

MAX

UNIT(1)

tw(INT)

Pulse duration, INT input low/high

Synchronous

2tc(SYSCLK)

cycles

With qualifier

tw(IQSW) + tw(SP) + 1tc(SYSCLK)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

7.9.7.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)

PARAMETER

MIN

MAX

UNIT

td(INT) Delay time, INT low/high to interrupt-vector fetch(2)

tw(IQSW) + 14tc(SYSCLK)

tw(IQSW) + tw(SP) + 14tc(SYSCLK)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.

(2)

This assumes that the ISR is in a single-cycle memory.

Interrupt Vector

XINT1, XINT2, XINT3,

XINT4, XINT5

Address bus

(internal)

w(INT)

d(INT)

Figure 7-16. External Interrupt Timing

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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