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TMS320F28076PZP bảng dữ liệu(PDF) 61 Page - Texas Instruments |
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TMS320F28076PZP bảng dữ liệu(HTML) 61 Page - Texas Instruments |
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61 / 192 page ![]() 7.9.7 Interrupts Figure 7-15 provides a high-level view of the interrupt architecture. As shown in Figure 7-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins. In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group. INPUTXBAR4 CPU1.W DINT CPU1.LPMINT CPU1.W AKEINT CPU1.TINT0 CPU1. ePIE INPUTXBAR13 INPUTXBAR5 INPUTXBAR6 INPUTXBAR14 GPIO0 GPIO1 ... ... GPIOx CPU1.TIMER0 CPU1.XINT1 Control CPU1.XINT5 Control CPU1.XINT3 Control CPU1.XINT4 Control CPU1.XINT2 Control Input X-BAR LPM Logic CPU1.WD IN T13 INT14 NMI CPU1 INT1 to INT12 CPU1.TINT1 CPU1.TIMER1 CPU1.TINT2 CPU1.TIMER2 CPU1.TINT2 CPU1.NMIWD Peripherals Figure 7-15. External and ePIE Interrupt Sources www.ti.com TMS320F28076, TMS320F28075 SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TMS320F28076 TMS320F28075 |
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