TMS320F28076PZP datasheet(65/192 Pages) TI

65 / 192 page

Section 7.9.8.3.3 shows the STANDBY mode timing requirements, Section 7.9.8.3.4 shows the switching

characteristics, and Figure 7-18 shows the timing diagram for STANDBY mode.

7.9.8.3.3 STANDBY Mode Timing Requirements

MIN

MAX

UNIT

tw(WAKE-INT)

Pulse duration, external

wake-up signal

QUALSTDBY = 0 | 2tc(OSCCLK)

3tc(OSCCLK)

cycles

QUALSTDBY > 0 |

(2 + QUALSTDBY)tc(OSCCLK) (1)

(2 + QUALSTDBY) * tc(OSCCLK)

(1)

QUALSTDBY is a 6-bit field in the LPMCR register.

7.9.8.3.4 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td(IDLE-XCOS)

Delay time, IDLE instruction executed to

XCLKOUT stop

16tc(INTOSC1)

cycles

td(WAKE-STBY)

Delay time, external wake signal to

program execution resume(1)

cycles

•

Wakeup from flash

–

Flash module in active state

175tc(SYSCLK) + tw(WAKE-INT)

•

Wakeup from flash

–

Flash module in sleep state

6700tc(SYSCLK) (2) + tw(WAKE-

INT)

•

Wakeup from RAM

3tc(OSC) + 15tc(SYSCLK) +

tw(WAKE-INT)

(1)

This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

(2)

This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and

FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2807x

Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 120 MHz, RWAIT is 2, and

FPAC1[PSLEEP] is 0x860.

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TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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