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TMS320F28076PZP bảng dữ liệu(PDF) 86 Page - Texas Instruments

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7.10.1.2.1 ADC Operating Conditions
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
UNIT
ADCCLK (derived from PERx.SYSCLK)
5
50
MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)
100
ns
VREFHI
2.4
2.5 or 3.0
VDDA
V
VREFLO
VSSA
0
VSSA
V
VREFHI – VREFLO
2.4
VDDA
V
ADC input conversion range
VREFLO
VREFHI
V
(1)
The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
TMS320F28076, TMS320F28075
SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021
www.ti.com
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28076 TMS320F28075



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