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TMS320F28076PZP bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TMS320F28076PZP bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 192 page ![]() 50 49 48 47 46 45 44 43 42 41 40 39 38 37 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 36 35 34 33 32 31 30 29 28 27 26 96 97 98 99 100 GPIO70 GPIO71 GPIO72 GPIO73 GPIO78 GPIO84 GPIO85 GPIO86 GPIO87 GPIO2 GPIO3 GPIO4 GPIO89 GPIO90 GPIO91 GPIO92 GPIO10 V DD V DD V DD V DDIO V DDIO V DDIO V DDIO V DD TCK TDO TDI FLT1 FLT2 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINB0 ADCIN15 ADCIN14 V DD V DD V SSA V DD3VFL V DDIO V DDA V REFHIB V SSA V REFLOB V DDIO TMS TRST A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name. Figure 6-2. 100-Pin PZP PowerPAD HTQFP (Top View) Note The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat from the die and to provide ground path for the digital ground (analog ground is provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this will provide both the digital ground path and good thermal conduction path. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this technology in mind. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD package. TMS320F28076, TMS320F28075 SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021 www.ti.com 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28076 TMS320F28075 |
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