TMS320F28076PZP datasheet(87/192 Pages) TI

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7.10.1.2.2 ADC Characteristics

over recommended operating conditions (unless otherwise noted)(5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC conversion cycles(1)

10.1

11 ADCCLKs

Power-up time

500

µs

Gain error

–5

±3

LSBs

Offset error

–4

±2

LSBs

Channel-to-channel gain error

±4

LSBs

Channel-to-channel offset error

±2

LSBs

ADC-to-ADC gain error

Identical VREFHI and VREFLO for all ADCs

±4

LSBs

ADC-to-ADC offset error

Identical VREFHI and VREFLO for all ADCs

±2

LSBs

DNL(2)

> –1

±0.5

LSBs

INL

–2

±1.0

LSBs

SNR(3) (10)

VREFHI = 2.5 V, fin = 100 kHz

68.8

THD(3) (10)

VREFHI = 2.5 V, fin = 100 kHz

–78.4

SFDR(3) (10)

VREFHI = 2.5 V, fin = 100 kHz

79.2

SINAD(3) (10)

VREFHI = 2.5 V, fin = 100 kHz

68.4

ENOB(3) (10)

VREFHI = 2.5 V, fin = 100 kHz,

single ADC(6), all packages

11.1

bits

VREFHI = 2.5 V, fin = 100 kHz,

synchronous ADCs(7), all packages

11.1

VREFHI = 2.5 V, fin = 100 kHz,

asynchronous ADCs(8),

100-pin PZP package

Not

supported

VREFHI = 2.5 V, fin = 100 kHz,

asynchronous ADCs(8),

176-pin PTP package

9.7

PSRR

VDDA = 3.3-V DC + 200 mV

DC up to Sine at 1 kHz

PSRR

VDDA = 3.3-V DC + 200 mV

Sine at 800 kHz

ADC-to-ADC isolation(10) (4) (9)

VREFHI = 2.5 V, synchronous ADCs(7), all

packages

–1

LSBs

VREFHI = 2.5 V, asynchronous ADCs(8),

100-pin PZP package

Not

supported

VREFHI = 2.5 V, asynchronous ADCs(8),

176-pin PTP package

–9

VREFHI input current

130

µA

(1)

See Section 7.10.1.2.5.

(2)

No missing codes.

(3)

AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source

for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip

Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.

(4)

Maximum DC code deviation due to operation of multiple ADCs simultaneously.

(5)

Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with

VREFHI = 2.5 V and VREFLO = 0 V.

(6)

One ADC operating while all other ADCs are idle.

(7)

All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.

(8)

Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.

(9)

Value based on characterization.

(10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and

crosstalk.

www.ti.com

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

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