iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

4.18. Typical Building Block Function Performance – LP Devices*

4.18.1. Pin-to-Pin Performance (LVCMOS25) – LP Devices

Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices

Function

Timing

Units

Basic Functions

16-bit decoder

11.0

ns

4:1 MUX

12.0

ns

16:1 MUX

13.0

ns

4.18.2. Register-to-Register Performance – LP Devices

Table 4.19. Register-to-Register Performance – LP Devices

Function

Timing

Units

Basic Functions

16:1 MUX

190

MHz

16-bit adder

160

MHz

16-bit counter

175

MHz

Embedded Memory Functions

256 x 16 Pseudo-Dual Port RAM

240

MHz

*Notes:



The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with device and tool

version. The tool uses internal parameters that have been characterized but are not tested on every device.



4.19. Typical Building Block Function Performance – HX Devices*

4.19.1. Pin-to-Pin Performance (LVCMOS25) – HX Devices

Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices

Function

Timing

Units

Basic Functions

16-bit decoder

10.0

ns

4:1 MUX

9.0

ns

16:1 MUX

9.5

ns