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ICE40LP bảng dữ liệu(PDF) 48 Page - Lattice Semiconductor

tên linh kiện ICE40LP
Giải thích chi tiết về linh kiện  iCE40 LP/HX Family
PDF  52 Pages
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ICE40LP bảng dữ liệu(HTML) 48 Page - Lattice Semiconductor

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iCE40 LP/HX Family
Data Sheet
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
FPGA-DS-02029-3.5
Revision History
Revision 3.5, September 2018
Section
Change Summary
All
Changed document number from DS1040 to FPGA-DS-02029.
Updated document template.
Pinout Information
Changed signal name from SPI_SS_B to SPI_SS in Signal Descriptions table.
Revision 3.4, October 2017
Section
Change Summary
Pin Information
Modified the dedicated inputs for Bank 1 of iCE40HX1K (CB132, TQ144), iCE40HX4K (CB132,
TQ144) and iCE40HX8K (CB132, CM225, CT256).
Revision 3.3, March 2017
Section
Change Summary
Introduction
Updated Features section. Added 121-ball caBGA package for ICE40 HX4K/8K to Table 1-1,
iCE40 LP/HX Family Selection Guide.
Architecture
Updated PLB Blocks section. Changed “subtracters” to “subtractors” in the Carry Logic
description.
Updated Clock/Control Distribution Network section. Switched the Clock Enable and the
Reset headings in Table 2-2, Global Buffer (GBUF) Connections to Programmable Logic
Blocks.
Pinout Information
Updated Pin Information Summary section. Added BG121information under iCE40HX4K and
iCE40HX8K.
Ordering Information
Updated iCE40 LP/HX Part Number Description section. Added Shipping Method and BG121
package under High Performance (HX) Devices.
Updated Ordering Information section. Added part numbers for BG121 under High-
Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging.
Supplemental Information
Corrected reference to “Package Diagrams Data Sheet”.
Revision 3.2, October 2015
Section
Change Summary
Introduction
Updated Features section. Added footnote to 16 WLCSP Programmable I/O: Max Inputs
(LVDS25) in Table 1-1, iCE40 LP/HX Family Selection Guide.
DC and Switching Characteristics
Updated sysCLOCK PLL Timing section. Changed tDT conditions.
Updated Programming NVCM Supply Current – LP Devices section. Changed IPP_2V5 and
ICCIO, ICC_SPI units.
Revision 3.1, March 2015
Section
Change Summary
DC and Switching Characteristics
Updated sysI/O Single-Ended DC Electrical Characteristics section. Changed LVCMOS 3.3 and
LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.



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