iCE40 LP/HX Family

Data Sheet

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.5

37

Symbol

Parameter

Min

Typ

Max

Unit

iCE40LP/HX4K - Medium Frequency

1200

—

—

us

iCE40LP/HX4K - high frequency

1200

—

—

us

iCE40LP/HX8K - Low Frequency (Default)

1200

—

—

us

iCE40LP/HX8K - Medium Frequency

1200

—

—

us

iCE40LP/HX8K - High Frequency

1200

—

—

us

Notes:

1.

Does not apply for NVCM.

2.

Supported only with 1.2 V V

CC

and at 25 °C.

3.

Extended range f

MAX

Write operations support up to 53 MHz only with 1.2 V V

CC

and at 25 °C.

4.28. Switching Test Conditions

Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are listed in Table 4.30.

DUT

R1

CL

Test Point

Figure 4.3. Output Test Load, LVCMOS Standards

Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces*

Test Condition

R1

CL

Timing Reference

VT

LVCMOS settings (L ≥ H, H ≥ L)

∞

0 pF

LVCMOS 3.3 = 1.5 V

—

—

—

LVCMOS 3.3 (Z ≥ H)

188

0 pF

1.5 V

LVCMOS 3.3 (Z ≥ L)

1.5 V

Other LVCMOS (Z ≥ H)

Other LVCMOS (Z ≥ L)

LVCMOS (H ≥ Z)

LVCMOS (L ≥ Z)

*Note: Output test conditions for all other interfaces are determined by the respective standards.