iCE40 LP/HX Family

Data Sheet

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16

FPGA-DS-02029-3.5

(1,0)

(1,0)

(1,0)

0

1

(1,0)

Pad

Pad

CLOCK_ENABLE

OUTPUT_ENABLE

OUTPUT_ENABLE

OUTPUT_CLK

INPUT_CLK

LATCH_INPUT_VALUE

LATCH_INPUT_VALUE

D_IN_1

D_IN_0

D_OUT_1

D_OUT_0

D_IN_1

D_IN_0

D_OUT_1

D_OUT_0

PIO Pair

0

1

= Statically defined by configuration program.

Figure 3.6. iCE I/O Register Block Diagram

Table 3.6. PIO Signal List

Pin Name

I/O Type

Description

OUTPUT_CLK

Input

Output register clock

CLOCK_ENABLE

Input

Clock enable

INPUT_CLK

Input

Input register clock

OUTPUT_ENABLE

Input

Output enable

D_OUT_0/1

Input

Data from the core

D_IN_0/1

Output

Data to the core

LATCH_INPUT_VALUE

Input

Latches/holds the Input Value