iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

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4.17. SubLVDS Emulation

The iCE40 LP/HX family supports the differential subLVDS standard. The output standard is emulated using

complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The

subLVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 4.2 is one

possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for

subLVDSE operation. Resistor values in Figure 4.2 are industry standard values for 1% resistors.

R

R

R

OD

OCM

V

CCIO

Differential

Output Pair

Figure 4.2. subLVDSE DC Conditions

Over recommended operating conditions.

Table 4.17. subLVDSE DC Conditions

Parameter

Description

Typ.

Units

Output impedance

20

Ω

Driver series resistor

270

Ω

Driver parallel resistor

120

Ω

Receiver termination

100

Ω

Output high voltage

1.43

V

Output low voltage

1.07

V

Output differential voltage

0.35

V

Output common mode voltage

0.9

V

Back impedance

100.5

Ω

DC output current

2.8

mA