TMS320F28375DPZP datasheet(104/222 Pages) TI1

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104

TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D

TMS320F28374D

Specifications

(1)

The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

Table 5-44. ADC Operating Conditions (12-Bit Single-Ended Mode)

over recommended operating conditions (unless otherwise noted)

MIN

TYP

MAX

UNIT

ADCCLK (derived from PERx.SYSCLK)

MHz

Sample window duration (set by ACQPS and PERx.SYSCLK)(1)

VREFHI

2.4

2.5 or 3.0

VDDA

VREFLO

VSSA

VREFHI – VREFLO

2.4

VDDA

ADC input conversion range

VREFLO

VREFHI

NOTE

The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input

exceeds this level, the VREF internal to the device may be disturbed, which can impact results

for other ADC or DAC inputs using the same VREF.

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