TMS320F28375DPZP datasheet(88/222 Pages) TI1

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TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Specifications

5.9.9.3

EMIF Electrical Data and Timing

5.9.9.3.1 Asynchronous RAM

Table 5-37 shows the EMIF asynchronous memory timing requirements. Table 5-38 shows the EMIF

asynchronous memory switching characteristics. Figure 5-21 through Figure 5-24 show the EMIF

asynchronous memory timing diagrams.

(1)

E = EMxCLK period in ns.

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended

wait states. Figure 5-22 and Figure 5-24 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Table 5-37. EMIF Asynchronous Memory Timing Requirements(1)

NO.

MIN

MAX

UNIT

Reads and Writes

EMIF clock period

tc(SYSCLK)

tw(EM_WAIT)

Pulse duration, EMxWAIT assertion and

deassertion

Reads

tsu(EMDV-EMOEH)

Setup time, EMxD[y:0] valid before EMxOE high

th(EMOEH-EMDIV)

Hold time, EMxD[y:0] valid after EMxOE high

tsu(EMOEL-EMWAIT)

Setup Time, EMxWAIT asserted before end of

Strobe Phase(2)

4E+20

Writes

tsu(EMWEL-EMWAIT)

Setup Time, EMxWAIT asserted before end of

Strobe Phase(2)

4E+20

(1)

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait

Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],

WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual

for more information.

(2)

E = EMxCLK period in ns.

(3)

EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The

maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the

TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.

Table 5-38. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)

NO.

PARAMETER

MIN

MAX

UNIT

Reads and Writes

td(TURNAROUND)

Turn around time

(TA)*E–3

(TA)*E+2

Reads

tc(EMRCYCLE)

EMIF read cycle time (EW = 0)

(RS+RST+RH+2)*E–3

(RS+RST+RH+2)*E+2

EMIF read cycle time (EW = 1)

(RS+RST+RH+2+

(EWC*16))*E–3

(RS+RST+RH+2+

(EWC*16))*E+2

tsu(EMCEL-EMOEL)

Output setup time, EMxCS[y:2] low

to EMxOE low (SS = 0)

(RS)*E–3

(RS)*E+2

Output setup time, EMxCS[y:2] low

to EMxOE low (SS = 1)

–3

th(EMOEH-EMCEH)

Output hold time, EMxOE high to

EMxCS[y:2] high (SS = 0)

(RH)*E–3

(RH)*E

Output hold time, EMxOE high to

EMxCS[y:2] high (SS = 1)

–3

tsu(EMBAV-EMOEL)

Output setup time, EMxBA[y:0]

valid to EMxOE low

(RS)*E–3

(RS)*E+2

th(EMOEH-EMBAIV)

Output hold time, EMxOE high to

EMxBA[y:0] invalid

(RH)*E–3

(RH)*E

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