TMS320F28375DPZP datasheet(34/222 Pages) TI1

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TMS320F28379D, TMS320F28378D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018

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TMS320F28374D

Terminal Configuration and Functions

Table 4-1. Signal Descriptions (continued)

TERMINAL

I/O/Z(1)

DESCRIPTION

NAME

MUX

POSITION

ZWT

BALL

NO.

PTP

NO.

PZP

NO.

GPIO156

0, 4, 8, 12

D12

–

I/O

General-purpose input/output 156

EPWM6B

Enhanced PWM6 output B (HRPWM-capable)

GPIO157

0, 4, 8, 12

B10

–

I/O

General-purpose input/output 157

EPWM7A

Enhanced PWM7 output A (HRPWM-capable)

GPIO158

0, 4, 8, 12

C10

–

I/O

General-purpose input/output 158

EPWM7B

Enhanced PWM7 output B (HRPWM-capable)

GPIO159

0, 4, 8, 12

D10

–

I/O

General-purpose input/output 159

EPWM8A

Enhanced PWM8 output A (HRPWM-capable)

GPIO160

0, 4, 8, 12

–

I/O

General-purpose input/output 160

EPWM8B

Enhanced PWM8 output B (HRPWM-capable)

GPIO161

0, 4, 8, 12

–

I/O

General-purpose input/output 161

EPWM9A

Enhanced PWM9 output A

GPIO162

0, 4, 8, 12

–

I/O

General-purpose input/output 162

EPWM9B

Enhanced PWM9 output B

GPIO163

0, 4, 8, 12

–

I/O

General-purpose input/output 163

EPWM10A

Enhanced PWM10 output A

GPIO164

0, 4, 8, 12

–

I/O

General-purpose input/output 164

EPWM10B

Enhanced PWM10 output B

GPIO165

0, 4, 8, 12

–

I/O

General-purpose input/output 165

EPWM11A

Enhanced PWM11 output A

GPIO166

0, 4, 8, 12

–

I/O

General-purpose input/output 166

EPWM11B

Enhanced PWM11 output B

GPIO167

0, 4, 8, 12

–

I/O

General-purpose input/output 167

EPWM12A

Enhanced PWM12 output A

GPIO168

0, 4, 8, 12

–

I/O

General-purpose input/output 168

EPWM12B

Enhanced PWM12 output B

RESET

XRS

F19

124

I/OD

Device Reset (in) and Watchdog Reset (out). The

devices have a built-in power-on reset (POR) circuit.

During a power-on condition, this pin is driven low by the

device. An external circuit may also drive this pin to

assert a device reset. This pin is also driven low by the

MCU when a watchdog reset or NMI watchdog reset

occurs. During watchdog reset, the XRS pin is driven low

for the watchdog reset duration of 512 OSCCLK cycles.

A resistor with a value from 2.2 kΩ to 10 kΩ should be

placed between XRS and VDDIO. If a capacitor is placed

between XRS and VSS for noise filtering, it should be

100 nF or smaller. These values will allow the watchdog

to properly drive the XRS pin to VOL within 512 OSCCLK

cycles when the watchdog reset is asserted. The output

buffer of this pin is an open drain with an internal pullup.

If this pin is driven by an external device, it should be

done using an open-drain device.

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