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TMS320F28375DPZP bảng dữ liệu(PDF) 61 Page - Texas Instruments |
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TMS320F28375DPZP bảng dữ liệu(HTML) 61 Page - Texas Instruments |
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61 / 222 page ![]() th(boot-mode)(A) XRS Boot-Mode Pins I/O Pins CPU Execution Phase Boot-ROM execution starts (initiated by any reset source) User-Code Execution Starts User Code Boot ROM User-Code Dependent User Code Peripheral/GPIO Function User-Code Dependent GPIO Pins as Input (Pullups are Disabled) GPIO Pins as Input Peripheral/GPIO Function tw(RSL2) th(boot-mode)(B) XRS (A) Boot-Mode Pins V V (3.3 V) DDIO DDA , V (1.2 V) DD User-code dependent Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input CPU Execution Phase Boot ROM User-code I/O Pins GPIO pins as input (pullups are disabled) User-code dependent tw(RSL1) 61 TMS320F28379D, TMS320F28378D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D www.ti.com SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Specifications Copyright © 2013–2018, Texas Instruments Incorporated A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 4-1. B. After reset from any source (see Section 5.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 5-5. Power-on Reset A. After reset from any source (see Section 5.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled. Figure 5-6. Warm Reset |
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