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TMS320F28375DPZP bảng dữ liệu(PDF) 36 Page - Texas Instruments

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TMS320F28375DPZP bảng dữ liệu(HTML) 36 Page - Texas Instruments

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TMS320F28379D, TMS320F28378D, TMS320F28377D
TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880K – DECEMBER 2013 – REVISED NOVEMBER 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320F28379D TMS320F28378D TMS320F28377D TMS320F28376D TMS320F28375D
TMS320F28374D
Terminal Configuration and Functions
Copyright © 2013–2018, Texas Instruments Incorporated
Table 4-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
NAME
MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
ANALOG, DIGITAL, AND I/O POWER
VDD
E9
16
16
1.2-V digital logic power pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 uF. The exact
value of the decoupling capacitance should be
determined by your system voltage regulation solution.
E11
21
39
F9
61
45
F11
76
63
G14
117
71
G15
126
78
J14
137
84
J15
153
89
K5
158
95
K6
169
–
P10
–
–
P13
–
–
R10
–
–
R13
–
–
VDD3VFL
R11
72
41
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin.
R12
–
–
VDDA
P6
36
18
3.3-V analog power pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
R6
54
38



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