UPD17P133CS datasheet(62/289 Pages) NEC

62 / 289 page

CHAPTER 7

SYSTEM REGISTER (SYSREG)

7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (Memory Pointer: MP)

7.5.1 Index Register (IX)

IX is used for address modification to data memory. It differs from MP in that its modification object is an address

that is specified as the bank or operand m.

As shown in Figure 7-7, IX is mapped to a total of 12 bits of system registers: 7AH (IXH), 7BH (IXM), and 7CH

(IXL). The index register enable flag (IXE) which enables address modification by IX is allocated to the lowest bit

of the PSW.

When IXE=1, an address in data memory specified with operand m is not m but the address indicated by the OR

of m, IXM and IXL. The bank specified at this time is that indicated by the OR of BANK and IXH.

Remark

The IXH of the

µPD17120 subseries is "fixed to 0" and therefore the bank is modified even when IXE=1

(thus preventing the bank from becoming other than 0).

7.5.2 Data Memory Row Address Pointer (Memory Pointer: MP)

MP is used for address modification to data memory. It differs from IX in that its modification object is the row

address of the address that is indirectly specified with the bank and operand @r.

As shown in Figure 7-7, MPH and IXH, and MPL and IXM, are respectively mapped to the same addresses (system

registers 7AH and 7BH). It is MPH's lower 3 bits and MPL's full 7 bits that are actually functioning as the MP. To

MPH's most significant bit is allocated the memory pointer enable flag (MPE) which enables address modification

by the MP.

When MPE=1, the bank and row address of the data memory indirectly specified with operand @r is not BANK

and mR but the address specified by the MP. (The column address is specified with the contents of r regardless

of the MPE.) At this time, MPH's lower 3 bits and MPL's most significant 4 bits point to BANK; and MPL's lower

3 bits point to the row address.

Remark

The MPH's lower 3 bits and MPL's most significant bit in the

µPD17120 subseries are "fixed to 0" and

therefore the bank is cleared to 0 even when MPE=1 (thus preventing the bank from becoming other

than 0).

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