DSP56857 datasheet(364/662 Pages) FREESCALE

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Interrupt Operation Description

5685X Digital Signal Controller User Manual, Rev. 4

12-64

Freescale Semiconductor

12.13.2 Receive Data (RX)

This interrupt can occur when receive interrupts are enabled via the RIE bit of the SCR2 register.

When a data word is ready to transfer from the RXSR register to the SRX register, and the ROE

bit is not set, an interrupt will occur indicating received data is available for processing. When the

Receive FIFO is enabled, this interrupt will not occur until the Receive Watermark level of the

FIFO is reached. If the FIFO is not enabled, an interrupt will occur for each data word received.

This interrupt is cleared by reading the SSR, verifying the RDR bit is set before reading the SRX

12.13.3 Receive Last Slot (RLS)

This interrupt occurs when the ESSI:

•

Is in the Network mode

•

Has been enabled via the RLIE bit of the SCR3 register

•

The last slot of the frame has ended

The RLS bit is also set at this time. This interrupt is generated regardless of the Receive Mask

Status Register (SSR).

12.13.4 Transmit Data With Exception

This interrupt can occur when transmit interrupts are enabled via the TIE bit of the SCR2 register.

When it is time to transfer data to the TXSR and data is not available in enabled STX or TXFIFO,

the TUE status bit is set and the transmit data exception interrupt occurs. The TUE bit, and its

interrupt, is cleared when the SSR is read then written to all the Transmit Data registers of the

enabled transmitters or when written to the STSR.

12.13.5 Transmit Data (TX)

This interrupt can occur when transmit interrupts are enabled via the TIE bit of the SCR2 register.

When data is transferred to the TXSR this interrupt will occur if more data is needed by any

enabled transmitter.

If the transmit FIFO is not enabled this interrupt will occur for each data word transmitted.

However, when the transmit FIFO is enabled, the interrupt will not occur until the Transmit

Watermark level is reached. This interrupt is cleared by reading the SSR and writing data to the

enabled STX registers. The interrupt may also be cleared by writing to the STSR.

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