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DSP56857 bảng dữ liệu(PDF) 330 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 330 Page - Freescale Semiconductor, Inc |
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330 / 662 page  Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00) 5685X Digital Signal Controller User Manual, Rev. 4 12-30 Freescale Semiconductor If the receive interrupt is enabled, it is asserted whenever the SRX is full and the data level in the ESSI receive FIFO reaches the selected threshold. If the receive FIFO feature is not enabled, this register is bypassed and the Receive Shift Register (RXSR) data is automatically transferred into the SRX. 12.8.6 ESSI Receive Shift Register (RXSR) This is a 16-bit shift register receiving incoming data from the serial receive data SRD pin. Data is shifted in by the selected internal/external bit clock when the associated internal/external frame sync is asserted. Data is assumed to be received MSB first if the RSHFD bit of the SCR3 is cleared, illustrated in Figure 12-18. If this bit is set, the data is received LSB first, as diagramed in Figure 12-19. Data is transferred to the ESSI Receive Data Register (SRX) or receive FIFO, if the receive FIFO is enabled and SRX is full, after 8, 10, 12, or 16 bits have been shifted in depending on the WL control bits. When receiving 8, 10, or 12 bits data, LSB bits are set to 0. Figure 12-18. Receive Data Path (RSHFD = 0) Figure 12-19. Receive Data Path (RSHFD = 1) SRX 15 0 16 bits RXD 87 8 bits 12 bits 10 bits 15 0 RXSR SRX 15 0 16 bits SRD 87 15 0 |
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