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DSP56857 bảng dữ liệu(PDF) 328 Page - Freescale Semiconductor, Inc

tên linh kiện DSP56857
Giải thích chi tiết về linh kiện  Digitial Signal Controller
PDF  662 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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DSP56857 bảng dữ liệu(HTML) 328 Page - Freescale Semiconductor, Inc

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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
5685X Digital Signal Controller User Manual, Rev. 4
12-28
Freescale Semiconductor
When both TXFIFO and STX are full, any further write will overwrite the content of TXFIFO
and STX.
Note:
Enable ESSI before writing to TXFIFO and STX.
12.8.3 ESSI Transmit Shift Registers (TXSR0, TXSR1, TXSR2)
The TXSR0-2 are 16-bit shift registers containing transmitted data. Data is shifted out to the
Serial Transmit Data (STD, SC0, and SC1) pins by the selected internal/external bit clock when
the associated internal/external frame sync is asserted. The Word Length (WL) control bits in the
ESSI Transmit Control Register (STXCR) determine the number of bits to be shifted out of the
TXSR0-2 registers before it is considered empty and can receive further writing. Please refer to
Section 12.8.11 for more information. This word length can be 8, 10, 12, or 16 bits. The data to
be transmitted occupies the most significant portion of the Shift register. The unused portion of
the register is ignored. Data is always shifted out of this register with the Most Significant Bit
(MSB) first when the TSHFD bit of the SCR2 is cleared, illustrated in Figure 12-15. If this bit is
set, the Least Significant Bit (LSB) is shifted out first, diagramed in Figure 12-16.
Figure 12-15. Transmit Data Path (TSHFD = 0)
STX
16 bits
8 bits
12 bits
10 bits
15
0
8
7
6
5
4
15
0
87
TXSR
STD



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