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DSP56857 bảng dữ liệu(PDF) 326 Page - Freescale Semiconductor, Inc

tên linh kiện DSP56857
Giải thích chi tiết về linh kiện  Digitial Signal Controller
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DSP56857 bảng dữ liệu(HTML) 326 Page - Freescale Semiconductor, Inc

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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
5685X Digital Signal Controller User Manual, Rev. 4
12-26
Freescale Semiconductor
12.8 Register Descriptions (ESSI0_BASE = $1FFE20,
ESSI1_BASE = $1FFE00)
All registers are addressed by word. Byte accesses to the registers are not supported. Eight
registers are not accessible. Registers associated with the Enhanced SSI (ESSI) are delineated in
the Memory Chapter, Table 3-16 and Table 3-17.
12.8.1 ESSI Transmit Registers (STX0, STX1, STX2)
The ESSI Transmit Data (STX02) are write-only 16-bit registers. Data to be transmitted is written
to these registers. If the Transmit FIFO Registers are utilized, data is transferred from the STX02
registers to the Transmit FIFO Register as the FIFOs have available space. Otherwise, data written
to these registers is transferred to the Transmit Shift Register (STX02) whenever the transmit
FIFO feature is enabled. When the feature is enabled, the Transmit Shift Registers (TXSR02)
receive their values from these FIFO registers. Transmitted data is first-in-first-out. If the transmit
FIFO feature is not enabled, this register is bypassed and the contents of the Transmit Data
Registers (STX02) is transferred into the Transmit Shift Registers (TXSR02). When the Transmit
Interrupt Enable (TIE) bit in SCR2 register is set the DSC is interrupted when the level of data in
an enabled transmit FIFO falls below the selected threshold and the Transmit Data Register Empty
(TDE) bit in the ESSI Status Register (SSR) is set.
When both Transmit FIFO and Transmit Data Registers are full, any further write will overwrite
the content of the Transmit Data Registers (STX02).
Add.
Offset
Register Name
15
14
13
12
11
10
98765
4321
0
$8
STXCR
R
PSR
WL
DC
PM
W
$9
SRXCR
R
PSR
WL
DC
PM
W
$A
STSR
R
W
DUMMY REGISTER WRITTEN DURING INACTIVE TIME SLOTS (NETWORK MODE)
$B
SFCSR
R
RFCNT
TFCNT
RFWM
TFWM
W
$C
TSMA
R
TSMA [15:0]
W
$D
TSMB
R
TSMB [31:16]
W
$E
RSMA
R
RSMA [15:0]
W
$F
RSMA
R
RSMB [31:16]
W
R
0
Read as 0
W
Reserved
Figure 12-11. ESSI Register Map Summary (Continued)



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