DSP56857 datasheet(332/662 Pages) FREESCALE

332 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-32

Freescale Semiconductor

Shift Register is transferred into the Receive Data Register. If it is not enabled, the IF0 bit is

cleared.

12.8.7.3 Reserved—Bit 13

This bit is reserved or not implemented. It cannot be read nor modified by writing.

12.8.7.4 Transmit FIFO Full (TFF)—Bit 12

This status bit allows monitoring when the Transmit FIFO is full. The state of this bit reflects the

status of the transmitter(s) selected by the TXSF0-2 control bits.

•

0 = Transmit FIFO can accept more data

•

1 = Transmit FIFO is full

12.8.7.5 Transmit Last Slot (TLS)—Bit 11

This is a status bit indicating the timing of the last transmit slot during the Network mode

operation. When this bit is set, the Transmit Last Slot Interrupt is asserted. The interrupt service

routine for this interrupt should read the Status Register, then write 1 to this bit to clear the

interrupt.

If the Transmit Last Slot Interrupt is not enabled, this bit can be read by the software to determine

the timing of the last slot. When the TLIE bit in the SCR3 register is disabled the status bit will

only be asserted during the last slot timing.

•

0 = Not currently transmitting the last time slot of the transmit frame

•

1 = Last slot of the transmit frame is currently being transmitted

12.8.7.6 Receive Last Slot (RLS)—Bit 10

This is a status bit indicating the timing of the last receive slot during the Network mode

operation. When this bit is set, the Receive Last Slot (RLS) interrupt bit is asserted. The interrupt

service routine for this interrupt should read the Status Register and then write 1 to this bit to

clear the interrupt.

If the RLS interrupt is not enabled, this bit can be read by the software to determine the timing of

the last slot. When the RLIE bit in the SCR3 register is disabled the status bit will only be

asserted during the last slot timing.

•

0 = Not currently receiving the last time slot of the receive frame

•

1 = Last slot of the receive frame is currently being received

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