DSP56857 datasheet(214/662 Pages) FREESCALE

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Resets

5685X Digital Signal Controller User Manual, Rev. 4

8-36

Freescale Semiconductor

8.10 Resets

8.10.1 Reset Handshake Timing

The ITCN provides the 56800E with a reset vector address on the VAB pins whenever RST is

asserted. The Reset Vector will be presented until the first rising clock edge after RST is

released. The general timing is shown in Figure 8-25.

Figure 8-25. Reset Interface

8.10.2 ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are

disabled except the core IRQs with fixed priorities. Those are:

•

Illegal Instruction

•

SW Interrupt 3

•

HW Stack Overflow

•

Misaligned Long Word Access

•

SW Interrupt 2

•

SW Interrupt 1

•

SW Interrupt 0

•

SW Interrupt LP

Core IRQs are enabled at their fixed priority levels.

8.11 Interrupts

8.11.1 Interrupt Handshake Timing

The control logic looks a the current interrupt processing level using the SR_REG[9:8] bits from

the 56800E core and determines if an interrupt request of sufficient priority exists to assert the

interrupt output to the core. Upon asserting INT to the core, the Interrupt Controller also asserts

new values for the IPIC_LEVEL pins. These pins indicate the priority level required to interrupt

CLK

VAB

reset_vector_adr

RES

PAB

read_adr

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