CS5484 datasheet(25/67 Pages) CIRRUS

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CS5484

DS981F3

5.7 Phase Sequence Detection

Polyphase meters using multiple CS5484 devices may

be configured to sense the succession of voltage

zero-crossings and determine which phase order is in

service. The phase sequence detection within CS5484

involves counting the number of OWR samples from a

starting point to the next voltage zero-crossing rising

edge or falling for each phase. By comparing the count

for each phase, the phase sequence can be easily

determined: the smallest count is first, and the largest

count is last.

The phase sequence detection and control (PSDC)

direction and count results. Writing '0' to bit DONE and

'10110' to bits CODE[4:0] of the PSDC register followed

by a falling edge on the RX pin will initiate the phase

sequence detection circuit. The RX pin must be held low

for a minimum of 500ns. When the device is in UART

mode, it is recommended that a 0xFF command be

written to all parts to start the phase sequence

detection. This command is ignored by the UART

interface and a checksum is not needed. Multiple

CS5484 devices in a polyphase meter must receive the

that

all

CS5484

devices

start

count

simultaneously. Bit DIR of the PSDC register specifies

the direction of the next zero-crossing at which the

count stops. If bit DIR is '0', the count stops at the next

negative-to-positive zero crossing. If bit DIR is '1', the

count

stops

the

positive-to-negative

zero-crossing. When the count stops, the DONE bit will

be set by the CS5484, and then the count result of each

phase may be read from bits PSCNT[6:0] of the PSDC

If the PSCNT[6:0] bits are equal to 0x00, 0x7F or

greater than 0x64 (for 50Hz) or 0x50 (for 60Hz), then a

measurement

error

has

occurred,

and

the

measurement results should be disregarded. This could

happen when the voltage input signal amplitude is lower

than the amplitude specified in the VZXLEVEL register.

To determine the phase order, the PSCNT[6:0] bit count

from each CS5484 is sorted in ascending order. Figure

16 and Figure 17 illustrate how phase sequence

detection is performed.

Phase sequences A, B, and C for the default rising edge

transition are illustrated in Figure 16. The PSCNT[6:0]

bits from the CS5484 on phase A will have the lowest

count, followed by the PSCNT[6:0] bits from the

CS5484 on phase B with the middle count, and the

PSCNT[6:0] bits from the CS5484 on phase C with the

highest count.

Phase sequences C, B, and A for rising edge transition

are illustrated in Figure 17. The PSCNT[6:0] bits from

the CS5484 on phase C will have the lowest count,

followed by the PSCNT[6:0] bits from the CS5484 on

phase B with the middle count, and the PSCNT[6:0] bits

from the CS5484 on phase A with the highest count.

5.8 Temperature Measurement

The CS5484 has an internal temperature sensor, which

is designed to measure temperature and optionally

compensate for temperature drift of the voltage

reference. Temperature measurements are stored in

the Temperature register (T), which, by default, is

configured to a range of ±128 degrees on the Celsius

(°C) scale.

The application program can change both the scale and

range of temperature by changing the Temperature

Gain (TGAIN) and Temperature Offset (TOFF) registers.

Figure 16. Phase Sequence A, B, C for Rising Edge Transition

-2

Phase A Channel

-2

Phase B Channel

-2

Phase C Channel

Write 0x16 to

PSDC Register

Start on the Falling

Edge on the RX Pin

Stop

Phase C Count

Phase B Count

Phase A Count

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