CS5484 datasheet(18/67 Pages) CIRRUS

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CS5484

DS981F3

Fine phase compensation control bits, FPCCx[8:0],

provide up to 1/OWR delay in the current channel.

Coarse phase compensation control bits, CPCCx[1:0],

provide an additional 1/OWR delay in the current

channels or up to 2/OWR delay in the voltage channel.

Negative delay in the voltage channel can be

implemented by setting longer delay in the current

channel than the voltage channel. For a OWR of

4000Hz, the delay range is ±500µs, a phase shift of

±8.99° at 50Hz and ±10.79° at 60 Hz. The step size is

0.008789° at 50 Hz and 0.010547° at 60Hz.

4.5 DC Offset and Gain Correction

The system and CS5484 inherently have component

tolerances, gain, and offset errors, which can be

removed using the gain and offset registers. Each

measurement channel has its own set of gain and offset

registers. For every instantaneous voltage and current

sample, the offset and gain values are used to correct

DC offset and gain errors in the channel (see section 7.

System Calibration on page 62 for more details).

4.6 High-pass and Phase Matching Filters

Optional high-pass filters (HPF in Figures 9 and 10)

remove any DC component from the selected signal

paths. Each power calculation contains a current and

voltage channel. If an HPF is enabled in only one

channel, a phase-matching filter (PMF) should be

applied to the other channel to match the phase

response of the HPF. For AC power measurement,

high-pass filters should be enabled on the voltage and

current channels. For information about how to enable

and disable the HPF or PMF on each channel, refer to

section 6.6.3 Configuration 2 (Config2) – Page 16,

Address 0 on page 38.

4.7 Digital Integrators

Optional digital integrators (INT in Figures 9 and 10) are

implemented on both current channels (I1, I2) to

compensate for the 90º phase shift and 20dB/decade

gain generated by the Rogowski coil current sensor.

When a Rogowski coil is used as the current sensor, the

integrator (INT) should be enabled on that current

channel. For information about how to enable and

disable the INT on each current channel, refer to section

6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on

page 38.

4.8 Low-rate Calculations

All the RMS and power results come from low-rate cal-

culations by averaging the output word rate (OWR) in-

stantaneous values over N samples, where N is the

value stored in the SampleCount register. The low-rate

interval or averaging period is N divided by OWR

(4000Hz if MCLK = 4.096MHz).

The CS5484 provides two averaging modes for low-rate

calculations: Fixed Number of Samples Averaging

mode and Line-cycle Synchronized Averaging mode.

By default, the CS5484 averages with the Fixed Num-

ber of Samples Averaging mode. By setting the

AVG_MODE bit in the Config2 register, the CS5484 will

use the Line-cycle Synchronized Averaging mode.

4.8.1 Fixed Number of Samples Averaging

N is the preset value in the SampleCount register and

should not be set less than 100. By default, the

SampleCount is 4000. With MCLK = 4.096MHz, the

averaging period is fixed at N/4000 = 1 second,

regardless of the line frequency.











Registers

...

APCM

Config 2

V1(V2)

I1 (I2)

P1 (P2)

Q1 (Q2)

I1ACOFF (I2ACOFF )

S1 (S2)



PF1 (PF2)

I1RMS (I2RMS)

V1RMS (V2RMS)

Q1AVG (Q2AVG)

P1AVG (P2AVG)

Q1OFF (Q2OFF)



P1OFF (P2OFF)



Inverse

Figure 11. Low-rate Calculations

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