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TLE5012B bảng dữ liệu(PDF) 15 Page - Infineon Technologies AG |
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TLE5012B bảng dữ liệu(HTML) 15 Page - Infineon Technologies AG |
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15 / 50 page ![]() TLE5012B Application Circuits Data Sheet 15 Rev. 2.0, 2014-02 3 Application Circuits The application circuits in this chapter show the various communication possibilities of the TLE5012B. The pin output mode configuration is device-specific and it can be either push-pull or open-drain. The bit IFAB_OD (register IFAB, 0DH) indicates the output mode for the IFA, IFB and IFC pins. The SSC pins are by default push- pull (bit SSC_OD, register MOD_3, 09H). Figure 3-1 shows a basic block diagram of a TLE5012B with Incremental Interface and SSC configuration. The derivate TLE5012B - E1000 is by default configured with push-pull IFA (IIF_A), IFB (IIF_ B) and IFC (IIF_IDX) pins. Figure 3-1 Application circuit for TLE5012B with IIF interface and SSC (using internal CLK) In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open-drain pins, three resistors (one for each line) between output line and VDD would be recommended (e.g. 2.2kΩ). Figure 3-2 shows a basic block diagram of the TLE5012B with HS Mode and SSC configuration. The derivate TLE5012B - E3005 is by default configurated with push-pull IFA (HS1), IFB (HS2) and IFC (HS3) pins. Figure 3-2 Application circuit for TLE5012B with HS Mode and SSC (using internal CLK) VRG VRA VRD TLE5012B X GMR Y GMR Temp SD- ADC SD- ADC SD- ADC SSC Interface Incremental IF PWM HSM Osc *) recommended , e.g. 100Ω 100nF IFC (IIF_IDX) VDD (3.0 – 5.5V) **) GND PLL CSQ SCK DATA IFA (IIF _A) IFB (IIF _B) SSC IIF **) recommended , e.g. 470Ω *) *) Digital Signal Processing Unit CORDIC CCU RAM ISM Fuses VRG VRA VRD TLE5012B X GMR Y GMR Temp SD- ADC SD- ADC SD- ADC SSC Interface Incremental IF PWM HSM Osc *) recommended , e.g. 100Ω 100nF IFC (HS3) VDD (3.0 – 5.5V) **) GND PLL CSQ SCK DATA IFA (HS1) IFB (HS2) SSC HSM **) recommended , e.g. 470Ω *) *) Digital Signal Processing Unit CORDIC CCU RAM ISM Fuses |
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